1. Field of the Invention
The present invention relates to a memory device and, more particularly, to a memory device typified by a thin film magnetic memory device, including a memory cell having an electric resistance value which varies according to the level of storage data.
2. Description of the Background Art
As a non-volatile memory device capable of storing data with low power consumption, attention is being paid to an MRAM (Magnetic Random Access Memory) device. The MRAM device is a non-volatile memory device for storing data by using a plurality of thin film magnetic elements formed on a semiconductor integrated circuit. Each of the thin film magnetic elements can be accessed at random.
Particularly, in recent years, it was announced that the performance of an MRAM device is dramatically improved by using a thin film magnetic element using a magnetic tunnel junction (MTJ) as a memory cell. An MRAM device including memory cells each having the magnetic tunnel junction is disclosed in technical document such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000 and xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 20 is a schematic diagram showing the configuration of a memory cell having a magnetic tunnel junction (hereinbelow, also simply called an MTJ memory cell).
Referring to FIG. 20, the MTJ memory cell has a magnetic tunnel junction MTJ in which a resistance value changes according to the level of storage data and an access transistor ATR. The access transistor ATR takes the form of a field effect transistor and is coupled between the magnetic tunnel junction MTJ and a ground voltage Vss.
For the MTJ memory cell, a write word line WWL for instructing data writing, a read word line RWL for instructing data reading, and a bit line BL as a data line for transmitting an electric signal corresponding to the level of the storage data at the time of data reading and data writing are disposed.
FIG. 21 is a conceptual diagram for explaining an operation of reading data from the MTJ memory cell.
Referring to FIG. 21, the magnetic tunnel junction MTJ has a magnetic layer having a fixed magnetic field in a fixed direction (hereinbelow, also simply called a fixed magnetic layer) FL and a magnetic layer having a free magnetic field (hereinbelow, also simply called a free magnetic layer) VL. Between the fixed magnetic layer FL and the free magnetic layer VL, a tunnel barrier TB formed by an insulating film is disposed. In the free magnetic layer VL, according to the level of storage data, either the magnetic field in the same direction as the fixed magnetic layer or the magnetic field in the direction different from the fixed magnetic layer FL is written in a non-volatile manner.
In a data reading operation, the access transistor ATR is turned on in response to activation of the read word line RWL. By the turn-on, a sense current Is supplied as a data read current at a fixed level is passed from a not-illustrated data read circuit to a current path constructed by the bit line BL, magnetic tunnel junction MTJ, access transistor ATR and ground voltage Vss.
The electric resistance value of the magnetic tunnel junction MTJ changes according to the relation between the magnetic field direction of the fixed magnetic layer FL and that of the free magnetic layer VL. To be specific, when the magnetic field direction of the fixed magnetic layer FL and that written in the free magnetic layer VL are the same, the electric resistance value of the magnetic tunnel junction MTJ is smaller as compared with the case where the magnetic field directions are different from each other.
In the data reading operation, therefore, a voltage drop occurring in the magnetic tunnel junction MTJ by the sense current Is varies according to the magnetic field direction stored in the free magnetic layer VL. Consequently, when the supply of the sense current Is is started after the bit line BL is once precharged to a high voltage, by detecting a change in voltage level of the bit line BL, data stored in the MTJ memory cell can be read.
FIG. 22 is a conceptual diagram for explaining a data writing operation to the MTJ memory cell.
Referring to FIG. 22, in the data writing operation, the read word line RWL is made inactive, and the access transistor ATR is turned off. In such a state, a data write current for writing the magnetic field to the free magnetic layer VL is passed to the write word line WWL and the bit line BL. The magnetic field direction of the free magnetic layer VL is determined by a combination of the direction of the data write current flowing in the write w word line WWL and the direction of the data write current flowing in the bit line BL.
FIG. 23 is a conceptual diagram for explaining the relation between the direction of the data write current and the magnetic field direction in the data writing operation.
Referring to FIG. 23, a magnetic field Hx on the lateral axis indicates the direction of a magnetic field H(WWL) generated by the data write current flowing in the write word line WWL. On the other hand, a magnetic field Hy on the vertical axis denotes a direction of the magnetic field H(BL) generated by the data write current flowing in the bit line BL.
The magnetic field direction stored in the free magnetic layer VL is newly written only when the sum of the magnetic fields H(WWL) and H(BL) reaches the area outside of the asteroid characteristic line shown in the diagram. That is, in the case where the magnetic field corresponding to the area inside the asteroid characteristic line is applied, the magnetic field direction stored in the free magnetic layer VL is not updated.
Therefore, in order to update the stored data in the magnetic tunnel junction MTJ by a writing operation, a current has to be passed to both the write word line WWL and the bit line BL. The magnetic field direction once stored in the magnetic tunnel junction MTJ, that is, storage data is held in a non-volatile manner until a new data writing operation is executed.
In the data reading operation as well, the sense current Is is passed through the bit line BL. The sense current Is is, however, generally set so as to be lower than the data write current by about one or two digits, the possibility that the stored data in the MTJ memory cell is erroneously rewritten by an influence of the sense current Is in the data reading operation is low.
The above-described technical documents discloses a technique of constructing an MRAM device as a random access memory (RAM) by integrating such MTJ memory cells on the semiconductor substrate.
FIG. 24 is a diagram showing the structure of the MTJ memory cell disposed on the semiconductor substrate.
Referring to FIG. 24, the access transistor ATR is formed in the p-type area PAR on a semiconductor main substrate SUB. The access transistor ATR has source/drain areas 110 and 120 as n-type areas and a gate 130. The source/drain area 110 is coupled to the ground voltage Vss via a metal line formed in a first metal wiring layer M1. As the write word line WWL, a metal wiring formed in a second metal wiring layer M2 is used. The bit line BL is formed in a third metal wiring layer M3.
The magnetic tunnel junction MTJ is disposed between the second metal wiring layer M2 in which the write word line WWL is provided and the third metal wiring layer M3 in which the bit line BL is provided. The source/drain area 120 of the access transistor ATR is electrically coupled to the magnetic tunnel junction MTJ via a metal film 150 formed in a contact hole, the first and second metal wiring layers M1 and M2, and a barrier metal 140. The barrier metal 140 is a buffer material provided to electrically couple the magnetic tunnel junction MTJ and a metal line.
As already described, in the MTJ memory cell, the read word line RWL is provided as a line independent of the write word line WWL. A data write current to generate a magnetic field of a magnitude of a predetermined value or larger has to be passed to the write word line WWL and the bit line BL in a data writing operation. The bit line BL and the write word line WWL are formed by using metal lines.
On the other hand, the read word line RWL is provided to control the gate voltage of the access transistor ATR, so that it is unnecessary to positively pass the current to the read word line RWL. From the viewpoint of improving the integration degree, without newly providing an independent metal wiring layer, the read word line RWL is formed in the same wiring layer as the gate 130 by using a polysilicon layer, a polycide structure, or the like.
Not only the MTJ memory cell but also a memory cell whose electric resistance value varies according to the level of storage data is generally used for a ROM (Read Only Memory) or RAM.
FIG. 25 is a block diagram for explaining the supply of a data read current to MTJ memory cells arranged in a matrix with high integration degree.
Referring to FIG. 25, in order to realize a highly integrated memory device, the MTJ memory cells are generally arranged in a matrix. FIG. 25 shows a case where the MTJ memory cells are arranged in n rows and m columns (n and m: natural numbers).
As already described, the bit line BL, write word line WWL, and read word line RWL are disposed for each of the MTJ memory cells. For the (n xc3x97m) MTJ memory cells arranged in the matrix, n write word lines WWL1 to WWLn, n read word lines RWL1 to RWLn, and m bit lines BL1 to BLm are disposed.
The data read current, that is, sense current Is at the time of data reading is supplied by a sense current supply circuit 500 disposed adjacent to the memory array. In the data reading operation, the read word line RWL corresponding to a selected memory cell row is selectively activated to the H level, and the sense current Is is supplied from the sense current supply circuit 500 to the bit line BL corresponding to the selected memory cell column. As described by referring to FIG. 21, in the selected memory cell MC, a voltage change according to the level of the stored data appears on the corresponding bit line.
In the configuration of FIG. 25, however, the length of a path through which the sense current Is passes on the bit line changes depending on the position of the selected memory cell row. There is a fear that the electric resistance value of the sense current path on the bit line changes according to the change in path length, and the value of the sense current Is fluctuates.
For example, in the configuration of FIG. 25, in the case where the n-th memory cell row close to the sense current supply circuit 500 is selected, a portion included in the sense current path (described as Isn in the drawing) on the bit line BL is short. Consequently, the electric resistance value of the sense current path is small.
On the contrary, when the first memory cell row on the side furthermost from the sense current supply circuit 500 is selected, the portion included in a sense current path (described as Is1 in the diagram) on the bit line BL is long. Consequently, the electric resistance value of the sense current path is large. Such a fluctuation in the electric resistance value of the sense current path causes a fluctuation in the sense current depending on the position of the selected memory cell row.
FIG. 26 is a block diagram showing a general configuration of the sense current supply circuit 500.
Referring to FIG. 26, generally, the sense current is supplied by a current supply unit 510 shared by the bit lines BL1 to BLm. The current supply unit 510 supplies the sense current Is to a data bus DB. The data bus DB is coupled to the bit lines BL1 to BLm via column selection gates CSG1 to CSGm.
Column selection lines CSL1 to CSLm are provided in correspondence with the memory cell columns and are selectively activated according to a column selection result. Each of the column selection gates CSG1 to CSGm is turned on when corresponding one of the column selection lines CSL1 to CSLm is activated. For example, the column selection gate CSG1 corresponding to the first memory cell column is turned on in response to activation (to the H level) of the corresponding column selection line CSL1 to thereby electrically couple the data bus DB and the bit line BL1. With respect to the subsequent memory cell columns as well, the column selection gates are similarly arranged.
With such a configuration, the current supply unit 510 is used in common by a plurality of bit lines in the memory array, and the sense current Is can be selectively supplied to the bit line corresponding to the selected memory cell column.
In the configuration of FIG. 26, however, the path length of the data bus DB for passing the sense current Is varies. There is the possibility that the electric resistance value of the sense current path on the data bus DB changes according to the change in the path length and the value of the sense current Is fluctuates.
For example, when the m-th memory cell column close to the current supply unit 510 is selected in the configuration of FIG. 26, the portion included in the sense current path on the data bus DB is short, so that its electric resistance value is small.
On the contrary, when the first memory cell column which is the furthermost from the current supply unit 510 is selected, the portion included in the sense current path on the data bus DB is long, so that its electric resistance value is large. Such a fluctuation of the electric resistance value of the sense current path causes a fluctuation in sense current depending on the position of the selected memory cell column.
In such a manner, in the MRAM device having a general configuration, the sense current may fluctuate depending on the position of the selected memory cell.
As already described, in the MRAM device having the MTJ memory cells, by detecting a voltage change which occurs according to the sense current Is and the electric resistance value of the MTJ memory cell, a data reading operation is executed. Consequently, the fluctuation in the sense current Is in a memory device having a memory cell whose electric resistance value changes according to the level of storage data, typified by the MTJ memory cell, checks a stable data reading operation.
Specifically, when the sense current fluctuates depending on the position of a selected memory cell, an operation margin in a data reading operation in the memory array cannot be maintained uniformly, and it becomes difficult to sufficiently assure the operation margin of the whole memory device. As a result, in the worst case, a problem such that an erroneous operation occurs and the yield deteriorates may arise.
In order to deal with such a problem, the level of the data read current can be finely adjusted according to the position of the selected memory cell. In this case, however, the configuration of a data read circuit becomes complicated, and a load on designing for the fine adjustment increases.
An object of the invention is to provide a memory device, typified by an MRAM device, having a memory cell whose electric resistance value changes according to the level of storage data, wherein a data read margin is maintained constant without depending on the position of a memory cell to be selected to thereby stabilize the data reading operation.
The present invention relates to, in short, a memory device having a memory array, a plurality of read word lines, a plurality of bit lines, a plurality of reference voltage lines, and a data read circuit. The memory array has a plurality of memory cells arranged in a matrix. The plurality of read word lines are provided in correspondence with rows of the memory cells and, in a data reading operation, are selectively activated in accordance with a row selection result. The plurality of bit lines are provided in correspondence with the columns of the memory cells. The plurality of reference voltage lines are disposed in correspondence with the columns in the same direction as the plurality of bit lines and supply a read reference voltage. In a data reading operation, the data read circuit supplies a data read current to be passed to a current path formed between the data read circuit and the read reference voltage to at least one of the plurality of bit lines which is selected in accordance with a column selection result. Each of the plurality of memory cells includes: a memory element whose electric resistance value changes according to a level of storage data; and a memory selection gate electrically coupled in series with the memory element between corresponding one of the plurality of bit lines and corresponding one of the plurality of reference voltage lines and turned on in response to activation of corresponding one of the plurality of read word lines. In the data reading operation, a sum of the electric resistance value in the reference voltage line and the electric resistance value of the bit line in a portion included in the current path, corresponding to a selected column, is almost constant without depending on the row selection result.
Thus, the major advantage of the invention is that, since the data read current can be maintained at a constant level without depending on the row to which the selected memory cell belongs, the operation margin in the data reading operation in the memory array can be maintained constant, and the data reading operation of the whole memory device can be stabilized.
According to another aspect of the invention, there is provided a w memory device including a memory array, a plurality of read word lines, a plurality of bit lines, a plurality of reference voltage lines, a data bus, a data read circuit, a column selection portion, and a pseudo data bus. The memory array has a plurality of memory cells arranged in a matrix. The plurality of read word lines are provided in correspondence with rows of the memory cells and selectively activated in accordance with a row selection result in a data reading operation. The plurality of bit lines are provided in correspondence with columns of the memory cells. The plurality of reference voltage lines are disposed in correspondence with the columns in the same direction as the plurality of bit lines and supply a read reference voltage. The data bus is disposed in the same direction as the plurality of word lines in an area adjacent to the memory array. The data read circuit supplies a data read current to be passed to a current path formed between the data read circuit and the read reference voltage to the data bus in the data reading operation. The column selection portion electrically couples one, selected according to a column selection result, of the plurality of bit lines and the data bus. The pseudo data bus is disposed in the same direction as the data bus in an area opposite to the data bus over the memory array. The pseudo data bus is electrically coupled to the read reference voltage and each of the reference voltage lines. Each of the plurality of memory cells includes: a memory element whose electric resistance value changes according to a level of storage data; and a memory selection gate electrically coupled in series with the memory element between corresponding one of the plurality of bit lines and corresponding one of the plurality of reference voltage lines and turned on in response to activation of corresponding one of the plurality of read word lines. In the data reading operation, a sum of the electric resistance value of the data bus and the electric resistance value of the pseudo data bus in a portion included in the current path is almost constant without depending on a the column selection result.
Thus, since the data read current can be maintained at a constant level without depending on the row to which the selected memory cell belongs, the operation margin in the data reading operation in the memory array can be maintained constant, and the data reading operation of the whole memory device can be stabilized.
According to further another aspect of the invention, there is provided a memory device including a memory array, a plurality of word lines, a plurality of bit lines, a plurality of word drivers, a data bus, a data read circuit, and a column selection element. The memory array has a plurality of memory cells arranged in a matrix. The plurality of word lines are provided in correspondence with rows of the memory cells. The plurality of bit lines are provided in correspondence with column of the memory cells. The plurality of word drivers are disposed in correspondence with the plurality of word lines. Each of the plurality of word drivers couples corresponding one of the plurality of read word lines to a read reference voltage in accordance with a row selection result in the data reading operation. The data bus is disposed in the same direction as the plurality of word lines in an area adjacent to the memory array. The data read circuit supplies a data read current to be passed to a current path formed between the data read circuit and the read reference voltage to the data bus in the data reading operation. The column selection element electrically couples at least one, selected according to a column selection result, of the plurality of bit lines and the data bus. Each of the plurality of memory cells includes: a memory element whose electric resistance value changes according to a level of storage data; and a rectifying device electrically coupled in series with the memory element between corresponding one of the plurality of bit lines and corresponding one of the plurality of word lines and turned on when the corresponding word line is coupled to the read reference voltage. In the data reading operation, a sum of an electric resistance value of the read word line corresponding to the selected row and an electric resistance value of the data bus in a portion included in the current path is almost constant without depending on the column selection result.
Thus, in the memory array in which the memory cells each using the rectifying device are arranged in a matrix, adapted to higher integration degree, without depending on the column to which the selected memory cell belongs, the data read current can be maintained at a constant level. As a result, the operation margin in the data reading operation in the memory array can be kept uniform, and the higher integration degree of the memory device and stabilization in the data reading operation can be realized.
According to further another aspect of the invention, there is provided a memory device including a memory array, a plurality of word lines, a plurality of bit lines, a reference voltage line, a plurality of word drivers, and a data read circuit. The memory array has a plurality of memory cells arranged in a matrix. The plurality of word lines are provided in correspondence with rows of the memory cells. The plurality of bit lines are provided in correspondence with columns of the memory cells. The reference voltage line is disposed in the same direction as the plurality of bit lines in an area adjacent to the memory array and supplies a read reference voltage. The plurality of word drivers are disposed in correspondence with the plurality of word lines. Each of the plurality of word drivers electrically couples corresponding one of the plurality of read word lines to the reference voltage line in accordance with a row selection result in the data reading operation. The data read circuit supplies a data read current to be passed to a current path formed between the data read circuit and the read reference voltage to at least one of the plurality of bit lines selected in accordance with a column selection result. Each of the plurality of memory cells includes: a memory element whose electric resistance value changes according to a level of storage data; and a rectifying device electrically coupled in series with the memory element between corresponding one of the plurality of bit lines and corresponding one of the plurality of read word lines and turned on when the corresponding word line is coupled to the read reference voltage. In the data reading operation, a sum of an electric resistance value of the bit line corresponding to the selected column and an electric resistance value of the reference voltage line in a portion included in the data read current path is almost constant without depending on a result of the row selection.
Thus, in the memory array in which the memory cells each using the rectifying device are arranged in a matrix, adapted to higher integration degree, without depending on the row to which the selected memory cell belongs, the data read current can be maintained at a constant level. As a result, the operation margin in the data reading operation in the memory array can be kept uniform, and the higher integration degree of the memory device and stabilization in the data reading operation can be realized.